Implementation of a 200 MSps 12-bit SAR ADC
Author
Summary, in English
Analog-to-digital converters (ADCs) with high conversion frequency, often
based on pipelined architectures, are used for measuring instruments, wireless
communication and video applications. Successive approximation register
(SAR) converters offer a compact and power efficient alternative but the
conversion speed is typically designed for lower frequencies. In this thesis
a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was
designed for a 28 nm CMOS technology.
The proposed design uses an efficient SAR algorithm (merged capacitor
switching procedure) to reduce power consumption due to capacitor charging
by 88 % compared to a conventional design, as well as reducing the total
capacitor area by half. Sampling switches were bootstrapped for increased
linearity compared to simple transmission gates. Another feature of the low
power design is a fully-dynamic comparator which does not require a preamplifier.
Pre-layout simulations of the SAR ADC with 800 MHz input frequency
shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR
of 75.3 dB. The total power consumption is 1.77 mW with an estimated value
of 500 W for the unimplemented digital logic. Calculation of the Schreier
figure-of-merit was done with an input signal at the Nyquist frequency. The
simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW
respectively, corresponding to a figure-of merit of 176.6 dB.
based on pipelined architectures, are used for measuring instruments, wireless
communication and video applications. Successive approximation register
(SAR) converters offer a compact and power efficient alternative but the
conversion speed is typically designed for lower frequencies. In this thesis
a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was
designed for a 28 nm CMOS technology.
The proposed design uses an efficient SAR algorithm (merged capacitor
switching procedure) to reduce power consumption due to capacitor charging
by 88 % compared to a conventional design, as well as reducing the total
capacitor area by half. Sampling switches were bootstrapped for increased
linearity compared to simple transmission gates. Another feature of the low
power design is a fully-dynamic comparator which does not require a preamplifier.
Pre-layout simulations of the SAR ADC with 800 MHz input frequency
shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR
of 75.3 dB. The total power consumption is 1.77 mW with an estimated value
of 500 W for the unimplemented digital logic. Calculation of the Schreier
figure-of-merit was done with an input signal at the Nyquist frequency. The
simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW
respectively, corresponding to a figure-of merit of 176.6 dB.
Publishing year
2015
Language
English
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Document type
Student publication for Master's degree (two years)
Topic
- Technology and Engineering
Keywords
- SAR
- ADC
- MCS
- converter
- circuit design
- capacitor
Supervisor
- Pietro Andreani
Scientific presentation